Method for storing path metrics in a viterbi decoder

ABSTRACT

For a Viterbi decoder, it is proposed to combine the butterfly structures of the corresponding trellis diagram in pairs in such a way that for each butterfly structure pair, the destination states of the two butterfly structures in the trellis diagram at the same time form starting states for two other butterfly structures. After the determination of the path metrics of the destination states of the two butterfly structures of a butterfly structure pair, in each case the path metrics of those two destination states of this butterfly structure pair which are the same time form starting states of another butterfly structure are then stored in the form of a common memory word.

[0001] The present invention relates to a method for storing pathmetrics in a Viterbi decoder according to the preamble of claim 1, themethod being able to be used in particular for Viterbi decoders inmobile radio receivers for decoding channel-coded mobile radio signals.

[0002] In most known digital mobile radio receivers, a Viterbi decoderis used. A Viterbi decoder is a so-called maximum likelihood decoder,which is generally used for decoding channel-coded, in particularconvolutionally coded, mobile radio signals. During the channel coding,in the transmitter redundant information is added to the symbols to betransmitted, in order to increase the transmission reliability. Duringthe transmission of a mobile radio signal, however, noise is superposedon said signal. The task of the receiver consists, therefore, in usingthe reception sequence to find, from all possible transmissionsequences, that transmission sequence which corresponds with maximumlikelihood to the actual transmission sequence. This task is undertakenby the Viterbi decoder.

[0003] The coding specification used during the channel coding can bedescribed by a corresponding trellis diagram. By calculating so-calledmetrics, the Viterbi decoder determines that path of the trellis diagramwhich has the largest or smallest path metric, depending on therespective configuration of the decoder. Using this path of the trellisdiagram, the decoded sequence can then be determined and output.

[0004] The principles of Viterbi decoding will be briefly explained inmore detail below.

[0005]FIG. 4 illustrates by way of example a trellis diagram with ineach case four different states at the instants t . . . t+3, whichcorrespond for example to the bit states “00”, “10”, “01” and “11”. Eachsymbol sequence is assigned a corresponding path in the trellis diagram.In this case, a path comprises a sequence of branches between twotemporally successive states. In this case, each branch symbolizes astate transition between two temporally successive states; for example,the upper branch preceding from a state corresponds to a receptionsymbol with the binary “0” and the lower branch proceeding from the samestate corresponds to a reception symbol with the binary value “1”. Eachof these state transitions to which a branch metric (EM) λ_(t) isallocated corresponds to a transmission symbol. The branch metric λ_(t)is defined as follows:

λ_(t) =[y′ _(t) −r _(t) ²]

[0006] In this case, r_(t) corresponds to the reception symbol at theinstant t and y′_(t) corresponds to the transmission symbol expected asa function thereof at the instant t.

[0007] Furthermore, a path metric of λ_(t) allocated to each paththrough the trellis diagram up to the instant or time step t.

[0008] The trellis diagram shown in FIG. 4 is, in particular, a trellisdiagram with a so-called “butterfly” structure. This means that in eachcase two states of a time step t+1 of the trellis diagram are allocatedtwo states of the preceding time step t, whose branches in each caselead to the first-mentioned states of the time step t1, in each case twobranch metrics of the branches proceeding from different states beingidentical. Thus, for example, the states which are shown in FIG. 4 andto which the path metrics λ_(t) ⁽¹⁾, λ_(t) ⁽³⁾, λ_(t+1) ⁽²⁾ and λ_(t+1)⁽³⁾ are allocated form a “butterfly” structure of this type, the branchmetric for the branch from the state with the path metric λ_(t) ⁽¹⁾ tothe state with the path metric λ_(t+1) ⁽²⁾ corresponding to the branchmetric λ_(t) ⁽³⁾ of the branch from the state with the path metric λ_(t)⁽³⁾ to the state with the path metric λ_(t+1) ⁽²⁾, while on the otherhand the branch metric or the branch from the state with the path metricλ_(t) ⁽¹⁾ to the state with the path metric λ_(t+1) ⁽³⁾ corresponds tothe branch metric λ_(t) ⁽¹⁾ of the branch from the state with the pathmetric λ_(t) ⁽³⁾ to the state with the path metric λ_(L+1) ⁽²⁾. In thiscase, λ_(t) ⁽¹⁾ generally designates the path metric allocated to thestate s in the time step t, while λ_(t) ^((s)) designates the branchmetric of the state transition corresponding to the signal s at theinstant t.

[0009] The Viterbi decoder must then use an algorithm corresponding tothe trellis diagram to determine that path which has the best pathmetric. As a rule, this is by definition the path having the smallestpath metric.

[0010] Each path metric of a path leading to a specific state iscomposed of the path metric of a temporally preceding state and thebranch metric of the branch leading from this preceding state to thespecific state. The consequence of this is that not all of the possiblepaths and path metrics of the trellis diagram have to be determined andevaluated. Instead, for each state and for each time step of the trellisdiagram, in each case that path which has the best path metric up tothat instant is determined. Only this path, which is designated as“survivor path”, and its path metric have to be stored. All other pathsleading to this state can be disregarded. Accordingly, during each timestep, there are a number of such survivor paths corresponding to thenumber of different states.

[0011] The above description makes it clear that the calculation of thepath metric λ_(t+1) ⁽¹⁾ depends on the path metrics of the path metricsof the preceding time step t, which are connected to the stats s via abranch. Accordingly, the calculation of the path metrics can be realizedby a recursive algorithm which is undertaken by a so-called “Add CompareSelect” unit (ACS unit) in a Viterbi decoder.

[0012]FIG. 5 illustrates the typical construction of a Viterbi decoder.

[0013] In addition to the ACS unit 2 with a memory or register 3, abranch metric unit (BMU) 1 and a survivor memory unit 4 are provided.The task of the branch metric unit is to calculate the branch metricsλ_(t) ⁽¹⁾ which are a measure of the difference between a receptionsymbol and that symbol which engenders the corresponding statetransition in the trellis diagram. The branch metrics calculated by thebranch metric unit 1 are fed to the ACS unit 2 for determination of theoptimal paths (survivor paths), the survivor memory unit 4 storing thesesurvivor paths, so that finally decoding can be carried out using thatsurvivor path which has the best path metric The symbol sequenceassigned to this path corresponds with maximum likelihood to thesequence actually transmitted.

[0014] The ACS unit 2 comprises a plurality of processor elements, as arule each state of the trellis diagram being evaluated by a separateprocessor element. The task of each individual processor elementconsists in selecting from two mutually competing paths (the so-called“competitor paths”) which lead to a state of the trellis diagram thepath (the so-called “survivor path”) having the best, i.e. smallest,path metric. The stored values for the survivor path leading to thisstate and its path metric are then updated.

[0015] As is evident from the trellis diagram shown in FIG. 4, eachstate s, at the instant t+1, is connected to a corresponding precedingstate via an upper branch and a lower branch. Consequently, in order todetermine the survivor path corresponding to this state s, the pathmetric of the path leading to the state s via the upper branch must becompared with the path metric of the path leading to the state s via thelower branch, i.e. the task of each processor element consists inselecting, for the purpose of determining the survivor path with thepath metric λ_(L+1) ⁽¹⁾ either the path which leads via the preceding“upper” state with the path metric λ_(t) ^((u)) and the “upper” branchwith the branch metric λ_(t) ^((u)) and whose path metric corresponds tothe sum λ_(t) ^((u))+λ_(t) ^((u)), or the path which leads via the“lower” state with the path metric λ_(t) ⁽¹⁾ and the “lower” branch withthe branch metric λ_(t) ⁽¹⁾ and whose path metric corresponds to the sumλ_(t) ⁽¹⁾+λ_(t) ⁽²⁾.

[0016] Since each result λ_(t) ⁽¹⁾ calculated for a state s in the timestep t is at the same time the basis for the calculation of a pathmetric or a temporally succeeding state, the feedback—shown in FIG. 5—ofthe ACS unit 2 via the memory 3 is necessary, the calculated pathmetrics being buffered in the memory 3.

[0017] The structure of the memory 3 must be configured in accordancewith the structure of the respective trellis diagram. During each symbolperiod, a number of path metrics corresponding to the number of statesof the trellis diagram must be read from the memory 3 and written to thememory 3. For each butterfly of the trellis diagram, two states areprocessed simultaneously, so that two starting path metrics must be readfrom the memory 3 and two path metrics calculated therefrom must bewritten to the memory 3.

[0018] This gives rise, however, to the problem that the path metricsmust not be overwritten before they have been read out.

[0019] In order to make this clearer, FIG. 6 illustrates a furthertrellis diagram with eight states. The trellis diagram has the butterflystructure already described, an exemplary butterfly being illustrated bybroken lines and comprising the starting states S_(t) No. 1 and 5 andthe destination states S_(t+1) No. 2 and 3. Consequently, for thecalculation of the path metrics of the destination states No. 2 and 3,the path metrics of the starting states No. 1 and 5 must first be readout.

[0020] This competition situation between the read-out operation and thewrite operation had led to a configuration of the memory 3 which is alsoknown as “ping-pong” implementation in the literature, the memory 3being subdivided into two memory banks, of which one is providedexclusively for read operations and the other is provided exclusivelyfor write operations.

[0021] Although undesirable collisions are reliably avoided with the aidof this technique, the memory 3 must nonetheless have twice the sizethat is inherently necessary, since both memory banks each have to beable to store the path metrics of all states S_(t) and S_(t+1).

[0022] A further problem associated with the storage of the path metricsis the mapping of the path metrics onto the memory, i.e. the assignmentof the individual path metrics to the different memory addresses.According to the prior art, this mapping has to be chosen in such a waythat different memory areas are used for the read and write operationsof the path metrics, in order to reliably avoid conflicts between theread and write operations.

[0023] The present invention is based on the object of proposing amethod for storing path metrics in a Viterbi decoder which can berealized with a lower memory requirement and reliably preventswrite/read conflicts.

[0024] This object is achieved according to the invention by means of amethod having the features of claim 1. The subclaims define advantageousand preferred embodiments or the present invention.

[0025] With the aid of the present invention, a method for storing pathmetrics in a Viterbi decoder is presented which is based on theprinciple of a time-variable trellis diagram and is suitable inparticular for trellis diagrams having a butterfly structure andcorresponding ACS units.

[0026] The method according to the invention requires just one memoryand enables path metrics to be read from and stored in the same memoryareas, i.e. the path metrics corresponding destination states calculatedon the basis of two starting path metrics are stored under the samememory address from which the two starting path metrics were previouslyread out. The size of the memory is independent of the respectivelychosen degree of parallelism of the trellis and merely has to correspondto the product of the number of different trellis states and the numberof bits per memory word. In particular, just one memory is necessaryeven when the path metrics for a plurality of processor elements areintended to be stored in combined form.

[0027] Write/read conflicts are reliably avoided.

[0028] The invention requires a minimal amount of area and powerconsumption of the chip used for Viterbi decoding, since just one memoryaddress is required for two path metrics. The invention is suitable bothfor feedforward codes, such as, for example, SDSL, and for feedbackcodes and allows the use of programmable Viterbi decoders, it beingpossible for the corresponding path metrics to be programed in a simplemanner for each butterfly.

[0029] The present invention is explained in more detail below using apreferred exemplary embodiment with reference to the accompanyingdrawing.

[0030]FIG. 1 shows an illustration for elucidating the principleunderlying the present invention for an SDSL Viterbi decoder on thebasis of a trellis comprising eight states,

[0031]FIG. 2 shows an illustration for elucidating a function which canbe used to determine, in a manner dependent on a counter reading, astate which, in accordance with a preferred exemplary embodiment of theinvention, is crucial for mapping the individual path metrics onto thedifferent memory addresses of the memory of the ACS unit,

[0032]FIG. 3 shows an illustration for elucidating a method from whichthe method according to the invention proceeds as a development,

[0033]FIG. 4 shows an exemplary trellis diagram with a butterflystructure and four states,

[0034]FIG. 5 shows the general construction of a Viterbi decoder, and

[0035]FIG. 6 shows the illustration of a trellis diagram with abutterfly structure for elucidating the problems associated with theprior art.

Before the details of the present invention are specifically discussed,the nomenclature that will be resorted to later in order to explain theinvention shall be briefly presented below.

[0036] If a trellis coder having a total memory size of M_(t) memorywords is assumed, a trellis code with M_(TS)=2^(MC) is obtained, whereN_(TS) designates the number of different states in the correspondingtrellis diagram. The length of the impulse response for a feedforwardcode having the code rate ½ is M_(T)+1. The state transitions in thetrellis diagram depend, as described, on the respectively coded bit B,the state S_(L+1) at the instant t+1 resulting from the preceding stateS_(t) in accordance with the following relationship:

S _((t))=(2·S ₁)mod(N _(TS) +B)

[0037] If the trellis diagram has the butterfly structure voice hasalready been described and is shown by way of example in FIG. 6, eachbutterfly is allocated two starting states and two destination states,it being possible, in each case with reference to the geometry of thetrellis, to distinguish between an upper state designated by the index(u) (for “upper”) and a lower state designated by the index (l) (for“lower”). In the case of the butterfly shown by broken lines in FIG. 6,it holds true that, for example, S_(t) ^((u))=1, S_(t) ⁽¹⁾=5, S_(L+1)^((u))=2 and S_(t+1) ⁽¹⁾=3, where S_(t) ^((u))=1, designate the startingstates and S_(t+1) ^((u)) and S_(t+1) ⁽¹⁾ designate the destinationstates of the corresponding butterfly.

[0038] As can also be gathered from the illustration of FIG. 6, thelower starting state S_(t) ⁽¹⁾ and the destination states S_(t+1) ^((u))and S_(t+1) ⁽¹⁾ of a butterfly depend on the upper starting state S_(t)^((u)), where the following relationships hold true:$O \leq S_{\tau}^{(u)} \leq {\frac{N_{TS}}{2} - 1}$$S_{l}^{(1)} = {S_{1}^{(u)} + \frac{N_{TS}}{2}}$

S ₁ ^((u))=(2·S ₁ ^((u)))mod(N _(TS)+0)

S _(t+1) ⁽¹⁾=(2·S ₁ ^((u)))mod(N _(TS)−1)=(2·S ₁ ^((l)))mod(N _(TS)+1)

[0039] Upon evaluation of the above formulae where N_(TS)=8 and S_(t)⁽¹⁾=1, the correct values S_(t) ⁽²⁾=5, S_(t+1) ^((u))=2 and S_(L+1)^((l))=3 result for the butterfly illustrated by broken lines in FIG. 6.

[0040] The present invention is based on the idea of storing the pathmetrics of a butterfly, which are calculated for the destination states,under the same memory address from which the corresponding starting pathmetrics were read out, thereby making it possible to avoid undesirableoverwriting of the path metrics in the memory 3. This measure results ina time-dependent variation of the trellis structure, so that theresultant trellis representation can also be designated as “time varyingtrellis” (TVT).

[0041] The TVT of the trellis structure shown in FIG. 6 is illustratedin FIG. 3. As is evident from FIG. 3, although the state transitions ofthe individual butterflies correspond to the state transitions shown inFIG. 6, with each time step or with each iteration the sequence of thestates is reordered in such a way that each destination state of abutterfly is connected to the corresponding starting scale of the samebutterfly by a horizontal branch. In FIG. 3, two butterflies areillustrated by dashed lines and dash-dotted lines, respectively, for theindividual iterations, said butterflies comprising the scarring statesNo. 2 and No. 6 and, respectively, No. 3 and No. 7 and the destinationstates No. 4 and No. 5 and, respectively, No. 6 and No. 7, so that theprinciple of the time-dependent reordering of the trellis structure canbe understood in particular using these butterflies.

[0042] Each line of the trellis shown in FIG. 3 corresponds to a memoryaddress of the memory 3, so that, for example, the path metrics for thestates No. 2, No. 4, No. 1 and No. 2 are successively written to one andthe same memory address (third line in the trellis diagram shown in FIG.3) . It can be shown that after M_(t) iterations (after M_(t)=3iterations in the example illustrated), the original state sequence isobtained again.

[0043] The previously described TVT approach prevents the undesirableoverwriting of path metrics in the memory 3. However, there is still theproblem that two path metrics must be read and written simultaneously inorder to enable the butterfly-structure-based calculation of the pathmetrics by the ACS unit 2, so that the memory would have to becorrespondingly subdivided. It can be shown that this is not possible,however, for the TVT approach.

[0044] Therefore, the TVT approach must be developed further to give anapproach which does justice to the butterfly structure and will beexplained below with reference to FIG. 1 and FIG. 2, and can also bedesignated as “butterfly oriented time varying trellis” (BFTVT).

[0045] The problem essentially associated with the previously describedTVT approach is that the path metrics—calculated by the ACS unit 2—ofthe destination states of a butterfly do not at the same time constitutestarting path metric, for a further butterfly. In order to clarify theseFacts, the starting and destination path metric pairs of a butterfly arerepresented below in the form [S_(t) ^((u)), S_(t) ⁽¹⁾] and [S_(t+1)^((u)), S_(t+1) ⁽¹⁾], respectively. Consequently, the following statetransitions result for the individual butterflies of the trellis shownin FIG. 3 (iteration 1):

[0046] [0,4]→[0,1]

[0047] [1,5]→[2,3]

[0048] [2,6 →[4,5]

[0049] [3,7]→[6,7]

[0050] It is evident that, for example, the destination states [0,1] ofthe butterfly with the starting states [0,4] do not simultaneouslyconstitute starting states for a common butterfly of the iteration 2. Itmakes no sense, therefore, to score the starting and destination pathmetrics of each butterfly in the form of a common memory word.

[0051] On the other hand, however, it is clear that, for example, thedestination states [0,1] and [4,5] of the two butterflies which have thestarting states [0,4] and [2,6] can at the same time be utilized asstarting states for subsequent butterflies in the trellis diagram havingthe starting states [0,4] and [1,5]. It can be proved that all 2^(MT−1)butterflies can be combined in pairs in such a way that the path metricsof the destination states of the butterfly pairs can as the same tine beutilized as starting path metrics for two other butterflies, if the pathmetrics determined for the destination states are correspondinglyreordered.

[0052] This approach is illustrated in FIG. 1. The word width of eachmemory word of the memory 3 is doubled compared with the prior art,thereby making it possible to store the results or path metrics of thedestination states of two butterflies in pairs of at least two pathmetrics per memory word. In particular, the size of the memory isindependent of the number of processor elements used; only the number ofwrite/read operations changes.

[0053] In FIG. 1, each circle corresponds to the two starting states orthe starting path metrics thereof of a corresponding butterfly in theform S^((u))/S⁽¹⁾. Combining the individual butterflies in pairsproduces the superordinate butterfly trellis structure shown in FIG. 1,the trellis shown in FIG. 1 defining which path metrics of thedestination scales of the original butterflies combined in pairs areused as starting path metrics or which subsequent butterflies. Thus,FIG. 1 illustrates, for example, a superordinate butterfly illustratedby broken lines, which, as described, combines the original butterflieswith the starting states 0,4] and [2,6], respectively, and thedestination states [0,1] and [4,5], respectively, and reorders theresultant destination states in pairs of [0,4] and [1,5], so that thesereordered destination state pairs can at the same time serve as startingstates for subsequent butterflies (cf. the butterfly structure of FIG.6, from which it is evident that the starting states [0,4] and [1,5] arerespectively assigned to a butterfly).

[0054] Furthermore, the superordinate trellis structure thus obtained isconstructed analogously to FIG. 3 in the form of a TVT structure.Consequently, each line of the trellis shown in FIG. 1 corresponds to amemory address of the memory 3, so that, for example with regard to thesecond line of the trellis illustrated, the path metrics of the statepairs [1,5], [2,6] and once again [1,5] are successively stored underone and the same memory address.

[0055] As can be gathered from the illustration of FIG. 1, the dimensionof the trellis is reduced to 2^(Mt−1) states on account of the pairwisecombination of the individual butterflies by comparison with FIG. 3, sothat the number of iterations which are necessary before the originalstate sequence is regained is also correspondingly reduced by the value1 by comparison with FIG. 3. The consequence of this is that theaddressing complexity with regard to the address generation for thememory 3 can also be correspondingly reduced.

[0056] It has been previously pointed out that all states of a butterflycan be derived front the upper starting state S^((u)) of this butterfly.The respectively suitable memory address for the path metric pairs shownin FIG. 1 can thus be determined in a relatively simple manner by usinga counter whose counter reading C varies between$\left\lbrack {{0\quad \ldots \quad \frac{N_{TS}}{2}} - 1} \right\rbrack,$

[0057] in which case, with the aid of a function f_(s(u))(C) in a mannerdependent thereon, the upper state S^((u)) of the butterfly pairrespectively corresponding to the instantaneous counter reading C isdetermined and then, with the aid of an addressing functionf_(addr)(S^((u)), I) in a manner dependent on the determined upper stateS^((u)) and the respective present iteration number I, the suitablememory address is determined. In the case where the path metrics of aplurality of processor elements are to be combined, the counter readingof the counter must vary between$\left\lbrack {{0\quad \ldots \quad \frac{N_{TS}}{2^{{Ic}{(N_{PE})}}}} - 1} \right\rbrack,$

[0058] where N_(PE) corresponds to the number of processor elements andld(X) corresponds to the expression log₁(X).

[0059] The function f_(s(u)) (C) is nonlinear. It can he shown that thisfunction can be realized in the form of a simple bit mapping, as isshown in FIG. 2, where MSB designates the most significant bit and LSBdesignates the least significant bit.

[0060] The addressing function f_(addr)(S^((u)), I) can be described onthe basis of the properties of a feedforward trellis coder by thefollowing relationship:

ADDR=[(2^(I) ·S ^((u)))mod(M _(T)−1)]+[2^((1−MT−1)) ·S ^((u))]

[0061] In this case, ADDR designates the memory address determined as afunction S^((u)), M_(t) and I for the respective path metric pair, whereIε[0 . . . M_(T)−1]. This addressing function can easily be implementedsince it merely corresponds to a (M_(T−1)) bit addition of the first andsecond terms represented, without a possible overflow having to be takeninto account. All multiplications within the formula represented can berealized by simple bit shifting operations.

[0062] In the case where the invention is to be applied to a pluralityof processor elements, the addressing function f_(addr)(S^((u)), I) canbe described by the following relationship:

ADDR=[(2¹ ·S ^((u)))mod(2^((1d(N) ^(_(TS)) ^()−└(N)_(Pr)−1))]+[2^((1d(N) _(Pr))−1−1c(N_(PR)−I)·S ^((u)])

[0063] The invention has been explained above with reference to the useof feedforward codes, for example an SDSL code. However, the inventioncan likewise be applied to feedback codes. Although the trellisstructure of a Vitrerbi decoder for feedback codes differs considerablyfrom that for feedforward codes, it is nonetheless the case for feedbackcodes, too, that in the trellis butterflies can be combined in pairs insuch a way that the corresponding path metrics of the destination statesat the same time constitute starting path metrics for two successivebutterflies in the trellis diagram. In contrast to feedforward codes,the number of iterations which are necessary before the original statesequence occurs again in the trellis diagram does not directly depend onthe value M_(T). For feedback codes, too, in an analogous manner to theprocedure described above for feedforward codes, correspondingexpressions for f_(s(u))(C) and f_(addr)(S^((u)), I) can be determined,the derivation of which is dispensed with, however, at this point.

1. A method for storing path metrics in a Viterbi decoder, the pathmetrics being determined using a trellis diagram which is allocated tothe Viterbi decoder and in which in each case two destination states ofa specific time step (t+1) form, with two starting states of a precedingtime step (t), a butterfly structure by means of which the correspondingtwo destination states of the specific time step (t+1) are connected tothe two starting states of the preceding time step (t) by means of arespective state transition branch, for each time step (t+1) the pathmetric (λ_(t+1)) of each destination state being determined as afunction of the path metrics (λ_(L)) of those starting states of thepreceding time step (t) which form a butterfly structure with therespective destination state, for this purpose the path metrics (λ_(t))of the corresponding two starting states being read from memory means(3), the path metric (λ_(t+1)) of the respective destination state ofthe time step (t+1) being determined as a function thereof and the pathmetric (λ_(t+1)) of the respective destination state being stored in thememory means (3), characterized in that the butterfly structures of thetrellis diagram of each time step (t) are combined at least in pairs insuch a way that for each butterfly structure pair of a tine step (t),the destination states of the two butterfly structures in the trellisdiagram at the same time form starting states for two butterflystructures of the subsequent rime step (t+1), and in that after thedetermination of the path metrics of the destination states of the twobutterfly structures of a butterfly structure pair, in each case thepath metrics of those two destination states of this butterfly structurepair which at the same time form starting states of a butterflystructure of a subsequent time step (t+1) are stored in the memory means(3) in the form of a common memory word.
 2. The method as claimed inclaim 1 , characterized in that in each case the path metrics of thosetwo starting states of a time step (t) which belong to the samebutterfly structure are stored in the form of a common memory word inthe memory means (3), and in that after the determination of the pathmetrics of the destination states of the two butterfly structures of abutterfly structure pair, in each case the path metrics of those twodestination states of this butterfly structure pair which at the sametime form the starting states of a butterfly structure of the subsequenttime step (t+1) are stored in the memory means (3) under the sameaddress as the path metrics of two starting states which form abutterfly structure with one of these two destination states.
 3. Themethod as claimed in claim 1 or 2 , characterized in that the pathmetric (λ_(t+1)) of each destination state is determined as a functionof the path metrics (λ_(t)) of the two starting states of thecorresponding butterfly structure, and also of branch metrics (λ_(t))which are allocated to the two state transition branches of thebutterfly structure.
 4. The method as claimed in claim 3 , characterizedin that, in each butterfly structure, a first branch metric for thestate transition branch connecting the first starting state to the firstdestination state and the state transition branch connecting the secondstarting state to the second destination state is of identicalmagnitude, and a second branch metric for the state transition branchconnecting the first starting state to the second starting destinationstate and the state transition branch connecting the second statingstate to the first destination state is of identical magnitude.
 5. Themethod as claimed in one of the preceding claims, characterized in thatthe method is employed for decoding a signal coded with a feedforwardcode.
 6. The method as claimed in claim 5 , characterized in that themethod is employed for decoding an SDSL-coded signal.
 7. The method asclaimed in one of claims 1-4, characterized in that the method isemployed for decoding a signal coded with a feedback code.